1. Field of the Invention
The present invention relates to a solid state imaging device of all pixel simultaneous read type in which signal charges of unit pixels are read out into a vertical transfer register simultaneously and independently, and relates to a method for driving such a solid state imaging device. In particular, the present invention relates to a solid state imaging device formed so that signal charges arranged in the horizontal direction may be reduced, and relates to a method for driving such a solid state imaging device.
2. Description of the Related Art
In recent years, it has been demanded to make it possible to display moving pictures on a monitor of a personal computer as well. In the current processing capability, however, it is difficult to display moving pictures on personal computers with a resolution close to that of television sets. For displaying image data taken in from, for example, a CCD camera, it is necessary to reduce frames and lower the frame rate, or maintain the frame rate and reduce image data. In the case where the frame rate has been lowered, however, smooth motions cannot be represented. Typically, therefore, pixels are reduced, i.e., the resolution is lowered. As for the conventional image change-over method, there was a method of simultaneously reading signal charges of all photodiodes and then reducing in a solid state imaging device, and a method of coping with it by using software processing on the personal computer. Prior to describing the conventional image change-over method, the conventional solid state imaging device will first be described.
FIG. 1 is a schematic top view showing the entire configuration of a conventional solid state imaging device of all pixel readout type. As shown in FIG. 1, the conventional solid state imaging device is formed by photodiodes 1 arranged in a matrix form to convert light to signal charges, optical black level regions 2 for forming a reference level of image signals, a vertical surplus charge sweeping out drain 3 and a horizontal surplus charge sweeping out drain 4 for sweeping away the surplus charge, vertical transfer registers 5 for reading out and transferring signal charges stored in the photodiodes 1, and a horizontal transfer register 6 for receiving the signal charges transferred through a vertical transfer register 5 and transferring the signal charges to an output amplifier 7. On the photodiodes 1, RGB filters are arranged by using, for example, the Bayer method.
FIGS. 2 and 3 are diagrams showing an electrode configuration of a connection part between the vertical transfer registers 5 and the horizontal transfer register 6 shown in FIG. 1. FIG. 2 is a top view. FIG. 3 is a sectional view along a line A-A' of FIG. 2. The vertical transfer registers 5 are driven by 4-phase clocks .phi.V1, .phi.V2, .phi.V3, and .phi.V4. Transfer electrodes to which the clock .phi.V1 is applied are formed by first polysilicon layer. Transfer electrodes to which the clocks .phi.V2 and .phi.V4 are applied are formed by second polysilicon layer. Transfer electrodes to which the clock .phi.V3 is applied are formed by third polysilicon layer. Transfer electrodes of a final stage to which .phi.V1 is applied form gates for the horizontal transfer register 6.
The horizontal transfer register 6 is driven by 2-phase clocks .phi.H1 and .phi.H2. Each of all transfer electrodes of the horizontal transfer register 6 is formed by the second polysilicon layer and the third polysilicon layer. An electrode portion of the second polysilicon layer forms a storage portion, and an electrode portion of the third polysilicon layer forms a barrier portion. The signal charge of a vertical transfer register is transferred to the horizontal transfer register in such a state that the clock .phi.H1 of the horizontal transfer register is kept at its high level. In other words, if .phi.V1 turns the high level in such a state that .phi.H1 is kept at its high level, then transfer of the signal charge to undersides of the transfer electrodes to which .phi.H1 has been applied is started. When .phi.V1 has become its low level, the transfer is completed.
Operation of the conventional solid state imaging device in the connection part between the vertical transfer registers 5 and the horizontal transfer register 6 will now be described by referring to FIGS. 4 to 6. FIG. 4 shows the pulse timing of the 4-phase clocks .phi.V1, .phi.V2, .phi.V3, and .phi.V4 applied to the transfer electrodes of the vertical transfer registers 5 and the 2-phase clocks .phi.H1 and .phi.H2 applied to the transfer electrodes of the horizontal transfer register 6. FIG. 5 shows how signal charge in a vertical transfer register 5 is transferred to the horizontal transfer register 6. FIG. 6 shows how signal charge in the horizontal transfer register 6 is transferred. Signal charges stored under the transfer electrodes to which .phi.V3 and .phi.V4 have been applied during t0 begin to be transferred to the undersides of transfer electrodes to which .phi.H1 is applied, when .phi.V1 becomes its high level during t1. If .phi.V3, .phi.V4, and .phi.V1 are changed to the low level in the cited order, signal charges are transferred to the undersides of the electrodes for .phi.H1. The signal charges stored under the electrodes for .phi.H1 are successively transferred in the horizontal transfer register by repetition of alternate high/low levels of .phi.H1 and .phi.H2.
At this time, signals R1, G1, R2, G2, R3, G3, R4 and G4 according to the RGB Bayer arrangement are transferred without destroying the order as shown in FIG. 6. An output waveform of an output amplifier 7 is shown in FIG. 7.
For implementing moving pictures with smooth motions on a personal computer monitor, it is necessary to reduce pixels and lower the image resolution as described above. As for methods for lowering the resolution, there are a method of temporarily recording image data in an external memory, then rearranging data so that filter pixels of the same color will adjoin each other, and treating adjoining data of the same color as one pixel, and a method of reducing one of adjoining data of the same color.
Means for lowering the resolution in the device itself will now be described. For example, in the case where the horizontal resolution is to be reduced to 1/2, there is used a method of, for example, leaving the center of the image and sweeping away half of the image located on the left and right sides as shown in FIG. 8. Every horizontal line, in this method, a first 1/4 portion is transferred at a speed twice the normal speed as a sweeping away region 9, and the data are passed through the output amplifier and then thrown away. The next central 1/2 portion is transferred at the normal speed as an effective region 8, and image data are obtained. A final 1/4 portion is transferred at a high speed in the same way as the first 1/4 portion and then thrown away.
In the above described conventional method of lowering the resolution of the horizontal direction by software means, it is necessary to record images temporarily in the external memory and then rearrange data at high speed. In the case where the processing speed of the apparatus cannot cope with this, therefore, the frame rate cannot be maintained consequently, resulting in a drawback.
Furthermore, in the case where the resolution is lowered in the device itself, it is necessary to transfer the 1/2 image data to be swept away, with high speed drive. Therefore, excessive performance is required of the device, resulting in a lowered yield. In addition, the power dissipation of the drive circuit becomes large. This results in a drawback of degraded performance when viewed as the apparatus.